Control method and circuit for stopping clock signal

ABSTRACT

When controlling a clock to a central processing unit, it is naturally preferable not to change existing circuits which are not related to the control of the clock. A clock control circuit inputs a clock input CLK, and generates a clock output CLKOUT for the central processing unit. In the clock control circuit, CLK is masked by a write operation to an internal register. CLKOUT is stopped by the mask operation. The mask operation is carefully designed to be initiated when the internal cycle of the central processing unit is detected. The resumption of the clock is initiated by interrupts.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a technique for controlling a clock signal, especially to a method and circuit for stopping a clock signal. This invention is applicable to a control method and circuit for providing a clock to a central processing unit.

[0003] 2. Description of the Related Art

[0004] Enormous improvement has been achieved for central processing units generally called CPU or MPU. The operational frequency of the fastest devices has reached the order of gigaherz. Although the frequency will be higher in future, there is a program that the power consumption of such devices will become greater in relation to the operational frequency as the central processing units are generally MOS devices. Improvement of performance causes the expansion of power consumption, which reduces the battery operation time of products to which the central processing units are applied. To solve this problem, it is known to control elaborately the clock for the central processing units. Low power design is often introduced by reducing the frequency of the clock based on the types of processes executed.

[0005] Japanese Laid-Open publication H8-314716 discloses a clock control method in which a clock stop controller, in collaboration with a bus controller, stops the provision of a central processing unit clock signal to the central processing unit core by continuously asserting a bus request signal responding to a write request to a certain address. To resume from the clock stop mode, the controller issues a bus acknowledge response signal responding to a predetermined asynchronous input signal thereby canceling the prohibition state of the central processing unit clock signal.

[0006] In the above-mentioned technique, however, it becomes necessary to redesign the bus controller which is originally not related to the control of the clock for the central processing unit. It is naturally desirable to modify or add a circuit directly related to the clock control while leaving other circuits around the central processing unit intact in terms of design efficiency and developing term. It is also desirable not to redesign the central processing unit itself only for the clock control purpose.

SUMMARY OF THE INVENTION

[0007] It is therefore an object of the present invention to control the clock for the central processing unit without modifying the unit itself or its peripherals. It is another object to control the clock for central processing units and the like which are designed employing an instruction set without any dedicated instructions such as HALT which can easily stop the clock. It is still another object to avoid undesirable operation when stopping the clock. It is yet another object to resume or restart the clock efficiently.

[0008] According to one aspect of the present invention, a clock control circuit connected to a central processing unit providing a clock thereto is provided. The circuit comprises a detector which detects the cycle of the central processing unit to become an internal cycle after the central processing unit has executed an instruction to write in a predetermined address; and a clock output unit which stops the clock to the central processing unit after the detection of said internal cycle.

[0009] ‘An internal cycle’ is generally a cycle in which a process is conducted inside the central processing unit. In this description, however, the internal cycle means not only the above-mentioned cycle but also any periods with no external bus access such as an idle state of the central processing unit. ‘An instruction’ instructs a write in to a predetermined address for example to stop the clock. By this instruction, it becomes easy to stop the clock even when any specific instructions such as HALT to stop the operation of the central processing unit are not provided.

[0010] ‘Write in a predetermined address’ may or may not require specific data to be written in the address. When arbitrary data is allowed, the process for stopping the clock is initiated triggered by the write-in operation itself. This aspect of the clock control circuit may be provided with a register which becomes the target for the write-in.

[0011] According to this aspect, clock stop control is realized without modifying the central processing unit nor its peripherals.

[0012] According to another aspect of the present invention, clock control method to provide a clock from a clock control circuit to a central processing unit is provided. The method comprises detecting a cycle of the central processing unit to become an internal cycle after the central processing unit has executed an instruction to write in a predetermined address; and stopping the clock to the central processing unit after the detection of said internal cycle, wherein the instruction is placed or put in an interrupt handler or routine which is initiated by a software interrupt to the central processing unit.

[0013] According to this aspect, a software interrupt can be used as a trigger for stopping the clock of the central processing unit and the whole process becomes easy. Further interrupt may be masked temporarily in the interrupt routine so that any undesirable stop of the clock is avoided during the interrupt processing.

[0014] This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 shows the pin attribute of a clock control circuit according to one embodiment of the present invention.

[0016]FIG. 2 shows the specification of a clock stop instruction register included in the clock control circuit according to one embodiment of the present invention.

[0017]FIG. 3 shows the signal connection between the clock control circuit and the central processing unit according to one embodiment of the present invention.

[0018]FIG. 4 is a schematic diagram corresponding to an internal cycle detection circuit and a circuit for stopping the clock.

[0019]FIG. 5 is a schematic diagram to stop and resume the clock.

[0020]FIG. 6 is a schematic diagram for outputting the clock.

[0021]FIG. 7 is a schematic diagram to generate the signals representing transfer types viewed from outside the central processing unit and the clock control circuit.

[0022]FIG. 8 is a timing chart showing the process of the clock control circuit according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The invention will now be described based on the preferred embodiments. This does not intend to limit the scope of the present invention, but exemplify the invention.

[0024]FIG. 1 shows the pin attribute of a clock control circuit according to one embodiment. CLK is a clock input to the circuit. CLKEN is a clock enable signal for the clock output from the circuit. nRESET is an active low reset signal (hereinafter active low signals are represented with ‘n’). CLKOUT is a clock output signal for the central processing unit or any other circuits. NIRQ and nFIQ are normal and fast interrupt request signals, respectively. ADDR [31:0] are 32 bits of address input. WRITE is an active high write command. SIZE [1:0] are data access width signals. TRANS [1:0] are 2 bit signals representing transfer types of the central processing unit. WDATA_0 is the bit 0 of a write data. TRANSOUT [1:0] are output signals generated from TRANSOUT [1:0] by the process described later. nFIQ is provided for time-critical interrupt process and is processed with higher priority than nIRQ. Hereinafter, CLKEN and CLKEN_DLY generated delaying CLKEN by one clock are fixed high throughout this description. [31:0], [1:0] and the like may be omitted.

[0025]FIG. 2 shows the specification of the ‘clock stop instruction register’ which is a system register equipped in the clock control circuit. This register is mapped in I/O area with its address being 14003000h. When ‘1’ is written in this register, this action is interpreted as the instruction for stopping the clock. Software interrupt is used as a trigger to stop the clock in this embodiment. The clock control circuit 10 enters an interrupt routine when a software interrupt instruction is executed. ‘An instruction to write ‘1’ to the clock stop instruction register’ is placed in the beginning part of the routine.

[0026] Subsequent interrupts may occur before the clock has stopped while the process of the routine is being appropriately executed. In such a situation, in order to process the interrupt correctly, it is necessary to avoid undesirable stop of the clock caused by a previous software interrupt. For this purpose, any further interrupt should be masked in the beginning portion of the interrupt routine so that further interrupts are blocked.

[0027]FIG. 3 is a signal connection diagram between clock control circuit 10 and CPU 20. The signals described in FIG. 1 are interconnected between the clock control circuit 10 and CPU 20. Several signals are connected to external circuits. For example, CLKEN, nRESET, nIRQ and nFIQ are inputted from an external circuit to the clock control circuit 10 and CPU 20. CLK is inputted to the clock control circuit 10 only. ADDR[31:0], WRITE, SIZE [1:0] and WDATA [0] are provided to external circuits from the CPU 20.

[0028] FIGS. 4 to 7 show circuits inside the clock control circuit 10.

[0029]FIGS. 4 and 5 correspond to an acknowledge circuit working from the clock stop instruction to the acknowledge of the instruction. As shown in FIG. 4, the decode signal of address ‘14003000h’, WRITE_PP which is a latched signal of WRITE when CLKEN is high, by D type flip-flop or DFF, CLKEN, and TRANS_PP1 described later are inputted to an AND 32. The output of the AND 32 is the select signal of a selector 33. When the select signal is ‘0’, the output of an AND 31 is selected and when the select signal is ‘1’, WDATA_(—)0 is selected. The selected signal is connected to the data input of a DFF 34. The DFF 34 acts as the ‘clock stop instruction register’. Hereinafter, unless otherwise described, nRESET signal is inputted to the reset pins and CLK is inputted to the clock input pins of DFFs. The output signal of the DFF 34 is CKSTOP signal. CKSTOP is inputted to one input pin of the AND 31 provided in front of the selector 33. Another input pin of the AND 31 is provided with the inverted signal of CKSTOPOK.

[0030] TRANS_PP are latched signals of TRANS when CLKEN is high, by a DFF. The bus cycle of CPU 20 is represented according to the timing of TRANS_PP. TRANS_PP0, 1 are inputted to a NOR 30, and the output of the NOR 30, I-CYC, is inputted to a 3-input AND 36.

[0031] I-CYC becomes active when the CPU 20 is in internal cycle. Here, the period when TRANS_PP0, 1 are both 0 is defined as an internal cycle.

[0032] The other two inputs of the AND 36 are CKSTOP and CLKEN_DLY which is a delayed signal of CLKEN by a DFF. The output of the AND 36 is CKSTOPOK. This signal becomes active only during the first one clock period during the process where the clock is effectively stopped thereby showing the start of the clock stop. CKSTOP is inputted to an inverter 38, and the output thereof is inputted to the AND 31. The DFF 34 is therefore set with WDATA_(—)0 when written from the CPU 20. Otherwise, if CKSTOPOK is high, the DFF 34 is set with ‘0’, and if not, DFF 34 preserves the previous value. The logic AND of I-CYC and CLKEN_DLY realized by the 3-input AND 36 indicates the state where ‘the cycle shown by TRANS was an internal cycle I and CLKEN was high in the preceding cycle’. This circuit is used to know in the cycle C4 that the above condition was met in the cycle C3 in FIG. 8 described later.

[0033]FIG. 5 is a circuit to generate CKSTOPPED which stays active while the clock is stopped, after receiving CKSTOPOK. nIRQ, nFIQ and CKSTOPPED are inputted to a 3-input AND 40. The output of the AND 40 becomes one input to an OR 42. CKSTOPOK is inputted to the other input of the OR 42. The output of the OR 42 is held for one clock period by a DFF 44 and becomes CKSTOPPED. Because CKSTOPOK can continuously be high only for one clock period, when either of nTRQ and nFIQ is asserted and the output of the 3-input AND 40 becomes low, CKSTOPPED becomes low promptly. As a result, the clock stop state is cancelled and normal operation is resumed.

[0034]FIG. 6 shows the configuration of a clock output circuit which stops the clock for the CPU 20 after the internal cycle of the CPU 20 is detected. CKSTOPOK becomes CKSTOPOK_DDLY via a delay gate 50. CKSTOPPED becomes CKSTOPPED_DDLY via a delay gate 54. The delay amount of these gates is described later. The two delay signals and CKSTOPPED are inputted to a 3-input OR 52, and the output of the OR 52, CKMASK, is inputted together with CLK to a 2-input OR 56. The output of the OR 56 is outputted to the CPU 20 as CLKOUT via an output buffer 58. CKMASK is a signal to mask or stop the clock.

[0035]FIG. 7 is a circuit to generate TRANSOUT used outside. TRANS_PP0, 1 are inputted to one input pin of 2-input AND 60, 64, respectively. The other input pins of the 2-input AND 60, 64 are provided with the inverted signal of CKMASK by an inverter 68. The output signals of the AND 60, 64 are outputted to external circuit as TRANSOUT0, 1 via output buffers 62, 66, respectively. The CPU 20 represents its bus cycle by TRANS. In this embodiment, however, the CPU 20 and the clock control circuit 10 are viewed from outside and the bus cycle realized by these two components is represented by TRANSOUT.

[0036] The operation to stop and resume the clock is as follows. Clock stop operation is conducted by a program of the CPU 20. When a software interrupt is occurred, the state of status registers, registers used in the software interrupt handler and a link register showing the return address is stored in a stack memory. During the software interrupt process, nIRQ is automatically disabled. nFIQ is, on the other hand, disabled beforehand in order to avoid an undesirable clock stop caused by nFIQ during the interrupt process before the complete stop of the clock. After nFIQ has been disabled, ‘1’ is written in the clock stop instruction register. The clock control circuit 10 stops the clock according to the instruction. CLKOUT is fixed high. During the stop clock period, TRANSOUT0,1 are fixed so that the bus cycle viewed outside the CPU 20 and the clock control circuit continues to be the internal cycle. By pretending to be the internal cycle, malfunction such as unexpected access to outside from the CPU 20 is avoided.

[0037] The clock restart process is initiated by either of nFIQ or nIRQ. The status and values of the status registers and other registers are read from the stack memory and the process returns from the software interrupt handler. The enable/disable state of nFIQ and nIRQ becomes back to the original state before the software interrupt has been initiated, by the mechanism of the CPU 20 automatically. When the interrupt is not prohibited, therefore, interrupt is handled. The clock is resumed even when the interrupt is prohibited from the beginning.

[0038]FIG. 8 is a timing chart for the stop and resumption of the clock by the clock control circuit 10. In this figure, C1-C13 stand for clock cycles. ‘N’ shown on TRANS corresponds to a cycle in which access is made by the CPU 20 to a certain address generating a bus access. ‘I’ shows an internal cycle of the CPU 20. The internal cycle for example corresponds to multiply instruction operation conducted inside the CPU 20. This signal becomes TRANS_PP latched by a DFF when CLKEN is high. The periods of ‘N’ and ‘I’ represented by TRANS_PP correspond to the periods of actual bus cycles.

[0039] In FIG. 8, CKSTOP changes to high in the period C2. This change shows that the write of ‘1’ to the clock stop instruction register is occurred. The periods C1, C2 are therefore in the interrupt routine.

[0040] CKSTOPOK then becomes high in the period C4 by the circuit shown in FIG. 4. This corresponds to the change of TRANS_PP to ‘I’ in this period. CKSTOP becomes low at the beginning of the period C5 as CKSTOPOK becomes high.

[0041] CKSTOPPED becomes high in the period of C5 after CKSTOPOK becomes high by the circuit shown in FIG. 5. The delayed signal of CKSTOPPED is CKSTOPPED_DDLY. CKSTOPPED becomes low at the beginning of the period of C11 by the circuit shown in FIG. 5 when either of nFIQ or nIRQ is asserted at the beginning of the period of C10. As a result, CKMASK stays high between the period C4 to C10 and CLKOUT is fixed high.

[0042] In this embodiment, delay is carefully designed not to cause a timing hazard for clock masking. T1 stands for the maximum delay of the paths starting from all CLKs of all DFFs which become the starting points of timing paths reaching CKSTOPOK to CLKOUT via the DFFs of starting points and CKSTOPOK_DDLY.

T1<(period when CLK is high)−(skew)

[0043] is met by circuit design. T2 stands for the maximum delay of the paths starting from CLK of DFF 44 via CKSTOPPED ending at CKMASK, except for the path through the delay gate 54 for CKSTOPPED_DDLY. T3 stands for the minimum delay of the paths starting from CLKs of all DFFs which become the starting points to reach CKSTOPOK ending at CKMASK via the DFFs of starting points and CKSTOPOK.

T2<T3−(skew)

[0044] is met by circuit design. T4 stands for the maximum delay of the paths starting from CLK ending at CLKOUT only via the OR 56 of FIG. 6 and the output buffer 58. T5 stands for the minimum delay of paths starting from CLK of the DFF 44 via the delay gate 54 of CKSTOPPED_DDLY ending at CLKOUT.

T4<T5−(skew)

[0045] is met by circuit design. The described timing design avoids the timing hazard. Here, ‘skew’ appears inside the clock control circuit 10.

[0046] In the above embodiment, the clock is stopped by writing ‘1’ to the clock stop instruction register. The clock may be stopped, however, triggered by any other hardware or software events.

[0047] Although the present invention has been described by way of exemplary embodiments, it should be understood that many changes and substitutions may be made by those skilled in the art without departing from the spirit and the scope of the present invention which is defined only by the appended claims. 

What is claimed is:
 1. Clock control circuit connected to a central processing unit providing a clock thereto, comprising: a detector which detects the cycle of the central processing unit to become an internal cycle after the central processing unit has executed an instruction to write in a predetermined address; and a clock output unit which stops the clock to the central processing unit after the detection of said internal cycle.
 2. The circuit of claim 1, further comprising a register to which write operation in the predetermined address is actually conducted.
 3. The circuit of claim 1, wherein said internal cycle corresponds to a period during which the central processing unit does not issue a bus access to external circuits.
 4. The circuit of claim 1, wherein whether said internal cycle is proceeding is judged by monitoring a signal representing transfer types of the central processing unit.
 5. The circuit of claim 1, wherein the instruction is placed in an interrupt routine initiated by a software interrupt to the central processing unit.
 6. The circuit of claim 1, further comprising a circuit which modifies and outputs a signal representing transfer types of the central processing unit so that said internal cycle is prolonged viewed from outside while the clock is stopped.
 7. The circuit of claim 1, wherein the detector is an acknowledge circuit which detects the acceptance of a request for the stop of the clock.
 8. The circuit of claim 1, further comprising a circuit which cancels the stop of the clock when an interrupt signal is asserted.
 9. The circuit of claim 1, wherein circuit timing is adjusted to avoid timing hazard when stopping the clock.
 10. Clock control method to provide a clock from a clock control circuit to a central processing unit, comprising: detecting a cycle of the central processing unit to become an internal cycle after the central processing unit has executed an instruction to write in a predetermined address; and stopping the clock to the central processing unit after the detection of said internal cycle, wherein the instruction is placed in an interrupt routine which is initiated by a software interrupt to the central processing unit.
 11. The method of claim 10, wherein the interrupt is temporarily masked in the interrupt routine.
 12. The method of claim 10, wherein whether said internal cycle is proceeding is judged by monitoring a signal representing transfer types of the central processing unit.
 13. The method of claim 10, further comprising detecting assertion of an interrupt signal and resuming the clock when the assertion of the interrupt signal is detected.
 14. The method of claim 10, wherein a signal representing transfer types of the central processing unit is modified and outputted so that the internal cycle of the central processing unit is prolonged viewed from outside. 